h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 819

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

26.6
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided
clock. The sampling frequency is set by the NESEL bit in LPWRCR.
The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
26.7
The clock select circuit selects the system clock that is used in this LSI.
Either a clock generated by an oscillator to which the EXTAL and XTAL pins are input or a 24-
MHz clock generated by multiplication in the PLL circuit is selected as a system clock when
returning from high-speed mode, medium-speed mode, sleep mode, or software standby mode. A
clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a
system clock when returning from the reset state or hardware standby mode.
A subclock input from the EXCL pin is selected as a system clock in subactive mode, subsleep
mode, or watch mode. At this time, modules such as the CPU, TMR_0, TMR_1, WDT_0,
WDT_1, ports, and interrupt controller and their functions operate depending on the SUB. The
count clock and sampling clock for each timer are divided SUB clocks.
26.8
This LSI incorporates a PLL circuit which generates a 48-MHz clock ( 48) or a 24-MHz clock
( 24) obtained by dividing the 48-MHz clock by two as the USB operating clock. The clock
source is the clock input from the USEXCL pin or the clock generated by an oscillator to which
the EXTAL and XTAL pins are input. The PLL input clock must be 8, 12, 16, 20, or 24 MHz. The
48-MHz clock input to the USEXCL pin can be directly used as the USB operating clock instead
Waveform Forming Circuit
Clock Select Circuit
PLL Circuit
EXCL
t
EXCLr
Figure 26.7 Subclock Input Timing
t
EXCLH
t
EXCLf
Rev. 3.00 Jan 25, 2006 page 767 of 872
t
EXCLL
Section 26 Clock Pulse Generator
V
CC
× 0.5
REJ09B0286-0300