h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 574

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 17 I
17.5.4
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
2. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
3. When the slave address matches in the first frame following the start condition, the device
4. At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Rev. 3.00 Jan 25, 2006 page 522 of 872
REJ09B0286-0300
(master output)
(master output)
(slave output)
User processing
according to the operating mode.
to 1.
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has
been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag
has been set to 1, the slave device drives SCL low from the fall of the receive clock until data
is read into ICDR.
SDA
SDA
SCL
ICDR
IRTR
IRIC
Data 2
Slave Receive Operation
2
Bit 0
C Bus Interface (IIC)
Figure 17.9 Master Receive Mode Operation Timing Example (2)
8
Data 1
[8]
[9] IRIC clear
A
[5]
9
[6] ICDR read
(Data 2)
Bit 7
(MLS = ACKB = 0, WAIT = 1)
1
Bit 6
2
Bit 5
[7] IRIC clear
3
Data 3
Data 2
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
8
[9] IRIC clear
[8]
[6] ICDR read
A
(Data 3)
[5]
9
Data 3
Bit 7
[7] IRIC clear
1
Data 4
Bit 6
2