h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 14

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h8s-2158

Manufacturer Part Number
h8s-2158
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Item
17.7 Usage Notes
Rev. 3.00 Jan 25, 2006 page xiv of lii
Page
550,
551
Revision (See Manual for Details)
16. Notes on Arbitration Lost
The I
frame as an address when arbitration is lost in master mode
and a transition to slave receive mode is automatically carried
out.
When arbitration is lost not in the first frame but in the second
frame or subsequent frame, transmit/receive data that is not an
address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the
address in the SAR or SARX register, the I
erroneously recognizes that the address call has occurred. (See
figure 17.29.)
In multi-master mode, a bus conflict could happen. When The
I
the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or
subsequent frame, take avoidance measures.
Figure 17.29 Diagram of Erroneous Operation when
Arbitration is Lost
Though it is prohibited in the normal I
problem may occur when the MST bit is erroneously set to 1
and a transition to master mode is occurred during data
transmission or reception in slave mode. In multi-master mode,
pay attention to the setting of the MST bit when a bus conflict
may occur. In this case, the MST bit in the ICCR register should
be set to 1 according to the order below.
(a) Make sure that the BBSY flag in the ICCR register is 0 and
the bus is free before setting the MST bit.
I
(Master transmit mode)
Other device
(Master transmit mode)
I
(Slave receive mode)
2
2
2
C bus interface
C bus interface
C bus interface is operated in master mode, check the state of
2
C bus interface recognizes the data in transmit/receive
S
S
S
• Receive address is ignored
SLA
SLA
SLA
Transmit data match
Transmit timing match
R/W
R/W
R/W
A
A
A
• Arbitration is lost
• The AL flag in ICSR is set to 1
• Automatically transferred to slave
• Receive data is recognized as
• When the receive data matches to
an address
the address set in the SAR or SARX
register, the I
as a slave device
receive mode
SLA
DATA1
DATA2
2
C protocol, the same
Transmit data does not match
2
C bus interface operates
R/W
2
C bus interface
A
A
DATA4
DATA3
Data contention
A
A

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