h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 473
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h8s-2158
Manufacturer Part Number
h8s-2158
Description
Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2158.pdf
(927 pages)
- Current page: 473 of 927
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Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
16.4.4
Serial Enhanced Mode Clock
SCI_0 and SCI_2 can be operated not only based on the clocks described in section 16.4.3, Clock,
but based on the following clocks, which are specified by the serial enhanced mode registers,
SEMR_0 and SEMR_2.
Double-Speed Operation: Operations that are usually achieved using the clock with frequency 16
times the normal bit rate can be achieved using the clock with frequency 8 times the bit rate in this
mode. That is, double transfer rate can be achieved using a single basic clock.
Double-speed operation can be specified by the ABCS bit in SEMR and is available for both clock
sources of an internal clock generated by the on-chip baud rate generator and an external clock
input at the SCK pin. However, double-speed operation cannot be specified when the average
transfer rate operation is selected.
Average Transfer Rate Operation: The SCI can be operated based on the clock with an average
transfer rate generated from the system clock instead of the external clock input at the SCK pin. In
this case, the SCK pin is fixed to input.
Average transfer rate operation can be specified by the ACS4 and ACS2 to ACS0 bits in SEMR.
Double-speed operation may be selected by clearing the ACS4 and ACS2 to ACS0 bits to 0.
Figures 16.6 and 16.7 show some examples of internal basic clock operations when average
transfer rate operation is selected.
Rev. 3.00 Jan 25, 2006 page 421 of 872
REJ09B0286-0300
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