h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 572

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 17 I
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
2. When ICDR is read (dummy data read), reception is started, and the receive clock is output,
3. The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. If the IEIC bit in ICCR has
4. Clear the IRIC flag to clear the wait state.
5. When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR
6. Read ICDR receive data.
7. Clear the IRIC flag to 0 to detect the next wait operation.
8. The IRIC flag is set to 1 at the fall of the 8th receive clock pulse.
9. Clear the IRIC flag in ICCR to cancel wait state.
10. Set the ACKB bit in ICSR to 1 so as to return the acknowledge data for the last reception.
11. Clear the IRIC flag to 0 to release the wait state.
12. When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
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Set the WAIT bit in ICMR to 1.
Clear the ACKB bit in ICSR to 0 (acknowledge data setting).
and data received, in synchronization with the internal clock.
In order to detect wait operation, clear the IRIC flag in ICCR to 0. After reading ICDR, clear
IRIC continuously so no other interrupt handling routine is executed. If the time for reception
of one frame of data has passed before the IRIC clearing, the end of reception cannot be
determined.
been set to 1, an interrupt request is sent to the CPU.
SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag
clearing. If the first frame is the last receive data, execute step [10] to halt reception.
The master device outputs the 9th clock and drives SDA low at the 9th receive clock pulse to
return an acknowledge signal.
are set to 1 at the rise of the 9th receive clock pulse. The master device outputs the receive
clock to receive the next data.
Data reception process from steps [5] to [7] should be executed during one byte reception
period after IRIC flag clearing in step [4] or [9] to release the wait state.
SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag
clearing. If this frame is the last receive data, execute step [10] to halt reception.
The master device outputs the 9th clock and drives SDA 1ow at the 9th receive clock pulse to
return an acknowledge signal.
Data can be received continuously by repeating steps [5] to [9].
Set the TRS bit in ICCR to 1 to switch from receive mode to transmit mode.
receive clock pulse.
2
C Bus Interface (IIC)