h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 541

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Note:
When the DTC is used, the IRIC flag is cleared automatically and transfer can be performed
continuously without CPU intervention.
When, with the I
other flags must be checked in order to identify the source that set the IRIC flag to 1. Although
each source has a corresponding flag, caution is needed at the end of a transfer.
When the ICDRE or ICDRF flag is set, the IRTR flag may or may not be set. The IRTR flag (the
DTC start request flag) is not set at the end of a data transfer up to detection of a retransmission
start condition or stop condition after a slave address (SVA) or general call address match in I
bus format slave mode.
Even when the IRIC flag and IRTR flag are set, the ICDRE or ICDRF flag may not be set. The
IRIC and IRTR flags are not cleared at the end of the specified number of transfers in continuous
transfer using the DTC. The ICDRE or ICDRF flag is cleared, however, since the specified
number of ICDR reads or writes have been completed. Table 17.4 shows the relationship between
the flags and the transfer states.
Bit
Bit Name
* Only 0 can be written, to clear the flag.
2
C bus format selected, the IRIC flag is set to 1 and an interrupt is generated,
Initial Value R/W
Description
Clocked synchronous serial format mode:
When the ICDRE or ICDRF flag is set to 1 in any
operating mode:
[Clearing conditions]
At the end of data transfer (rise of the 8th
transmit/receive clock with serial format selected)
When a start condition is detected with serial format
selected
When a start condition is detected in transmit mode
(when a start condition is detected in transmit mode
and the ICDRE flag is set to 1)
When data is transferred among the ICDR register
and buffer (when data is transferred from the transmit
buffer to the shift register in transmit mode and the
ICDRE flag is set to 1, or when data is transferred
from the shift register to the receive buffer in receive
mode and the ICDRF flag is set to 1)
When 0 is written in IRIC after reading IRIC = 1
When ICDR is read from or written to by the DTC
(This may not function as a clearing condition
depending on the situation. For details, see the
description of the DTC operation given below.)
Rev. 3.00 Jan 25, 2006 page 489 of 872
Section 17 I
2
C Bus Interface (IIC)
REJ09B0286-0300
2
C