h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 833

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 27 Power-Down Modes
27.3
Medium-Speed Mode
The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends
according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU
operates on the operating clock ( /2, /4, /8, /16, or /32) specified by the SCK2 to SCK0 bits.
The bus masters other than the CPU (DTC or RFU) also operate in medium-speed mode when the
DTSPEED bit in SBYCR is cleared to 0. Note however that the DTSPEED bit must be set to 1
when the RFU is used in medium-speed mode. On-chip peripheral modules other than the bus
masters always operate on the system clock ( ).
When the DTSPEED bit in SBYCR or the EXCKS bit in BCSR2 is set to 1, the clock can be
used as the DTC/RFU operating clock or external extended area bus cycle clock.
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if /4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
By clearing all of bits SCK2 to SCK0 to 0, a transition is made to high-speed mode at the end of
the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and the LSON
bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by
an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the
SSBY bit set to 1, the LSON bit cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0,
operation shifts to software standby mode. When software standby mode is cleared by an external
interrupt, medium-speed mode is restored.
When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 27.2 shows an example of medium-speed mode timing.
Rev. 3.00 Jan 25, 2006 page 781 of 872
REJ09B0286-0300