s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 588

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

CACHES, WRITE BUFFER
CACHE COHERENCE
The ICache and DCache contain copies of information normally held in main memory. If these copies of memory
information get out of step with each other because one is updated and the others are not updated, they are said to
have become incoherent. If the DCache contains a line which has been modified by a store or swap instruction, and
the main memory has not been updated, the cache line is said to be dirty. Clean operations force the cache to write
dirty lines back to main memory.
On the ARM920T, software is responsible for maintaining coherence between main memory, the ICache and the
DCache.
Register 7: Cache operations on page 2-15 describes facilities for invalidating the entire ICache or individual ICache
lines, and for cleaning or invalidating DCache lines, or for invalidating the entire DCache.
To clean the entire DCache efficiently, software should loop though each cache entry using the clean D single entry
(using index) operation or the clean and invalidate D entry (using index) operation. This should be performed by a
two-level nested loop going though each index value for each segment. See Data cache organization on page 4-9.
DCache, ICache, and memory coherence is generally achieved by:
Software can minimize the performance penalties of cleaning and invalidating caches by:
The ICache needs to be made coherent with a changed area of memory after any changes to the instructions which
appear at a virtual address, and before the new instructions are executed.
Dirty data in the DCache can be pushed out to main memory by cleaning the cache.
4-10
cleaning the DCache to ensure memory is up to date with all changes
invalidating the ICache to ensure that the ICache is forced to re-load instructions from memory.
Cleaning only small portions of the cache when only a small area of memory needs to be made coherent, for
example, when updating an exception vector entry.
Invalidating only small portions of the ICache when only a small number of instructions are modified, for example,
when updating an exception vector entry.
Not invalidating the ICache in situations where it is known that the modified area of memory cannot be in the
cache, for example, when mapping a new page into the currently running process.
ARM920T PROCESSOR