s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 30

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

Figure
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S3C2410A MICROPROCESSOR
ARM9TDMI Implementation Option........................................................................2-2
CP15 Register Map .............................................................................................2-4
CP15 Abbreviations .............................................................................................2-5
Address Types in ARM920...................................................................................2-6
Register 0: ID Code .............................................................................................2-7
Cache Type Register Format ................................................................................2-8
Cache Size Encoding ..........................................................................................2-9
Cache associativity encoding................................................................................2-9
Line Length Encoding ..........................................................................................2-10
Control Register 1-bit Functions ............................................................................2-11
Clocking Modes ..................................................................................................2-11
Register 2: Translation Table Base........................................................................2-12
Register 3: Domain Access Control.......................................................................2-13
Fault Status Register...........................................................................................2-14
Function Descriptions Register 7 ..........................................................................2-15
Cache Operations Register 7................................................................................2-16
TLB Operations Register 8 ...................................................................................2-18
Accessing the Cache Lock Down Register 9..........................................................2-20
Accessing the TLB Lock Down Register 10............................................................2-21
CP15 Register Functions .....................................................................................3-3
Interpreting Level One Descriptor Bits [1:0] ............................................................3-8
Interpreting Page Table Entry Bits 1:0 ...................................................................3-11
Priority Encoding of Fault Status...........................................................................3-18
Interpreting Access Control Bits in Domain Access Control Register........................3-19
Interpreting Access Permission (AP) Bits ..............................................................3-20
Data Cache and Write Buffer Configuration.............................................................4-7
ARM920T Clocking..............................................................................................5-1
Synchronous Clocking Mode ................................................................................5-2
Switching from FCLK to BCLK in Synchronous Mode .............................................5-2
Asynchronous Clocking Mode ..............................................................................5-3
Switching from FCLK to BCLK in Asynchronous Mode............................................5-3
List of Table
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