s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 120

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM INSTRUCTION SET
ASSEMBLER SYNTAX
<LDR|STR>{cond}<H|SH|SB> Rd,<address>
LDR
STR
{cond}
H
SB
SH
Rd
<address> can be:
1
2
3
4
{!}
3-38
Load from memory into a register
Store from a register into memory
Two-character condition mnemonic. See Table 3-2..
Transfer halfword quantity
Load sign extended byte (Only valid for LDR)
Load sign extended halfword (Only valid for LDR)
An expression evaluating to a valid register number.
An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base and a
corrected immediate offset to address the location given by evaluating the expression.
This will be a PC relative, pre-indexed address. If the address is out of range, an error will
be generated.
A pre-indexed addressing specification:
[Rn]
[Rn,<#expression>]{!}
[Rn,{+/-}Rm]{!}
A post-indexed addressing specification:
[Rn],<#expression>
[Rn],{+/-}Rm
Rn and Rm are expressions evaluating to a register number. If Rn is R15 then the
assembler will subtract 8 from the offset value to allow for ARM920T pipelining. In this
case base write-back should not be specified.
Writes back the base register (set the W bit) if ! is present.
offset of zero
offset of <expression> bytes
offset of +/- contents of index register
offset of <expression> bytes
offset of +/- contents of index register.
S3C2410A