s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 339

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) (Continued)
IN_PKT_RDY
IN_CSR2_REG
AUTO_SET
ISO
MODE_IN
IN_DMA_INT_EN
Reserved
IN_CSR1_REG
IN_CSR2_REG
Register
[3:0]
0x5200018B(B)
0x52000188(L)
Bit
Bit
[0]
[7]
[6]
[5]
[4]
Address
R/SET
MCU
MCU
R/W
R/W
R/W
R/W
–
CLEAR
(byte)
USB
R/W
R/W
USB
R
R
R
R
–
Set by the MCU after writing a packet of data
into the FIFO.
The USB clears this bit once the packet has
been successfully sent to the host.
An interrupt is generated when the USB clears
this bit, so the MCU can load the next packet.
While this bit is set, the MCU will not be able
to write to the FIFO.
If the MCU sets SEND STALL bit, this bit
cannot be set.
IN END POINT control status register2
If set, whenever the MCU writes MAXP data,
IN_PKT_RDY will automatically be set by the
core without any intervention from MCU.
If the MCU writes less than MAXP data,
IN_PKT_RDY bit has to be set by the MCU.
Used only for endpoints whose transfer type is
programmable.
1: Reserved
0: Configures endpoint to Bulk mode
Used only for endpoints whose direction is
programmable.
1: Configures Endpoint Direction as IN
0: Configures Endpoint Direction as OUT
Determine whether the interrupt should be
issued or not, when the IN_PKT_RDY
condition happens. This is only useful for DMA
mode.
0 = Interrupt enable,
Description
Description
Description
–
1 = Interrupt Disable
Reset Value
Initial State
Initial State
USB DEVICE
0x20
0
0
0
1
0
–
13-15