s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 227

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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S3C2410A
POWER MANAGEMENT
The power management block controls the system clocks by software for the reduction of power consumption in the
S3C2410A. These schemes are related to PLL, clock control logics (FCLK, HCLK, and PCLK) and wakeup signals.
Figure 7-7 shows the clock distribution of the S3C2410A.
The S3C2410A has four power modes. The following section describes each power management mode. The
transition between the modes is not allowed freely. For available transitions among the modes, see Figure 7-8.
Input Clock
FCLK defination
If SLOW mode
If Normal mode (P, M & S value)
FCLK = input clock/divider ratio
FCLK = MPLL clock (Mpll)
Figure 7-7. The Clock Distribution Block Diagram
Management
Clock Control
Register
Power
FCLK
HCLK
PCLK
UCLK (48 MHz)
ARM920T
Nand Flash
MEMCNTL
BUSCNTL
ARB/DMA
ExtMaster
LCDCNTL
Controller
INTCNTL
Host I/F
USB
CLOCK & POWER MANAGEMENT
Device
UART
PWM
GPIO
WDT
ADC
RTC
USB
SPI
I2C
SDI
I2S
7-9

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