s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 544

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

PROGRAMMER'S MODEL
The function of each cache operation is selected by the opcode_2 and CRm fields in the MCR instruction used to
write CP15 register 7. Writing other opcode_2 or CRm values is unpredictable.
Reading from CP15 register 7 is unpredictable.
Table 2-16 on page 2-16 shows instructions that can be used to perform cache operations with register 7
NOTES:
1.
2.
2-16
Invalidate ICache & DCache
Invalidate ICache
Invalidate ICache single entry (using MVA)
Prefetch ICache line (using MVA)
Invalidate DCache
Invalidate DCache single entry (using MVA)
Clean DCache single entry (using MVA)
Clean and Invalidate DCache entry (using MVA)
Clean DCache single entry (using index)
Clean and Invalidate DCache entry (using index)
Drain write buffer (1)
Wait for interrupt (2)
Will stop execution until the write buffer has drained.
Will stop execution in a LOW power state until an interrupt occurs.
Function
Table 2-16. Cache Operations Register 7
SBZ
SBZ
MVA format
MVA format
SBZ
MVA format
MVA format
MVA format
Index format
Index format
SBZ
SBZ
Data
MCR p15,0,Rd,c7,c7,0
MCR p15,0,Rd,c7,c5,0
MCR p15,0,Rd,c7,c5,1
MCR p15,0,Rd,c7,c13,1
MCR p15,0,Rd,c7,c6,0
MCR p15,0,Rd,c7,c6,1
MCR p15,0,Rd,c7,c10,1
MCR p15,0,Rd,c7,c14,1
MCR p15,0,Rd,c7,c10,2
MCR p15,0,Rd,c7,c14,2
MCR p15,0,Rd,c7,c10,4
MCR p15,0,Rd,c7,c0,4
Instruction
ARM920T PROCESSOR