s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 233
s3c2410a
Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C2410A.pdf
(599 pages)
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S3C2410A
Procedure to Wake-up from Power_OFF mode
1. The internal reset signal will be asserted if one of the wake-up sources is issued. This reset duration is
2. Check GSTATUS2[2] in order to know whether or not the power-up is caused by the wake-up from Power_OFF
3. Release the SDRAM signal protection by setting MISCCR[19:17]=000b.
4. Configure the SDRAM memory controller.
5. Wait until the SDRAM self-refresh is released. Mostly SDRAM needs the refresh cycle of all SDRAM row.
6. The information in GSTATUS3,4 can be used for user's own purpose because the value in GSTATUS3,4 has
7. – For EINT[3:0], check the SRCPND register.
Pin States in Power_OFF Mode
The pin state of the Power_OFF mode is as follows;
GPIO output pin
GPIO input pin
GPIO bi-directional pin
Function output pin
Function input pin
determined by the internal 16-bit counter logic and the reset assertion time is calculated as tRST = (65535 /
XTAL_frequency).
mode.
been preserved during Power_OFF mode.
– For EINT[15:4], check the EINTPEND instead of SRCPND (SRCPND will not be set although some bits of
– For alarm wake-up, check the RTC time because the RTC bit of SRCPND isn't set at the alarm wake-up.
– If there was the nBATT_FLT assertion during POWER_OFF mode, the corresponding bit of SRCPND has
EINTPEND are set.).
been set.
Pin Type
GPB0: output
GPB0: input
GPG6:SPIMOSI
nGCS0
nWAIT
Pin Example
Output ( GPIO data register value is used.)
Input
Input
Output (the last output level is held.)
Input
Pin States in Power_OFF Mode
CLOCK & POWER MANAGEMENT
7-15
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