s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 180

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

THUMB INSTRUCTION SET
FORMAT 16: CONDITIONAL BRANCH
OPERATION
The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes.
The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of
the current instruction.
The THUMB assembler syntax is shown in the following table.
4-34
0000
0001
0010
0011
0100
0101
0110
0111
1000
L
BEQ label
BNE label
BCS label
BCC label
BMI label
BPL label
BVS label
BVC label
BHI label
15
1
THUMB assembler
14
1
13
0
12
1
Table 4-17. The Conditional Branch Instructions
11
BEQ label
BNE label
BCS label
BCC label
BMI label
BPL label
BVS label
BVC label
BHI label
Cond
[7:0] 8-bit Signed Immediate
[11:8] Condition
ARM equivalent
Figure 4-17. Format 16
8
7
Branch if Z set (equal)
Branch if Z clear (not equal)
Branch if C set (unsigned higher or same)
Branch if C clear (unsigned lower)
Branch if N set (negative)
Branch if N clear (positive or zero)
Branch if V set (overflow)
Branch if V clear (no overflow)
Branch if C set and Z clear (unsigned higher)
SOffset 8
Action
0
S3C2410A