s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 184

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

THUMB INSTRUCTION SET
FORMAT 19: LONG BRANCH WITH LINK
OPERATION
This format specifies a long branch with link.
The assembler splits the 23-bit two's complement half-word offset specified by the label into two 11-bit halves,
ignoring bit 0 (which must be 0), and creates two THUMB instructions.
Instruction 1 (H = 0)
In the first instruction the Offset field contains the upper 11 bits of the target address. This is shifted left by 12 bits
and added to the current PC address. The resulting address is placed in LR.
Instruction 2 (H =1)
In the second instruction the Offset field contains an 11-bit representation lower half of the target address. This is
shifted left by 1 bit and added to LR. LR, which now contains the full 23-bit address, is placed in PC, the address of
the instruction following the BL is placed in LR and bit 0 of LR is set.
The branch offset must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of
the current instruction
4-38
15
1
14
1
13
1
12
1
11
H
[10:0] Long Branch and Link Offset High/Low
[11] Low/High Offset Bit
0 = Offset high
1 = Offset low
10
Figure 4-20. Format 19
Offset
0
S3C2410A