s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 251

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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S3C2410A
DMA STATUS (DSTAT) REGISTER
DMA CURRENT SOURCE (DCSRC) REGISTER
STAT
CURR_TC
CURR_SRC
Register
Register
DCSRC0
DCSRC1
DCSRC2
DCSRC3
DCSRCn
DSTATn
DSTAT0
DSTAT1
DSTAT2
DSTAT3
0x4B0000D4
0x4B0000D8
0x4B000014
0x4B000054
0x4B000094
[21:20]
0x4B000018
0x4B000058
0x4B000098
[19:0]
[30:0]
Address
Address
Bit
Bit
Status of this DMA controller.
00: Indicates that DMA controller is ready for another DMA request.
01: Indicates that DMA controller is busy for transfers.
Current value of transfer count.
Note that transfer count is initially set to the value of DCONn[19:0]
register and decreased by one at the end of every atomic transfer.
Current source address for DMAn
R/W
R/W
R
R
R
R
R
R
R
R
DMA 0 count register
DMA 1 count register
DMA 2 count register
DMA 3 count register
DMA 0 current Source Register
DMA 1 current Source Register
DMA 2 current Source Register
DMA 3 current Source Register
Description
Description
Description
Description
Reset Value
Reset Value
Initial State
Initial State
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
000000h
000000h
000000h
000000h
00000h
00b
DMA
8-11

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