s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 482

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

SPI INTERFACE
SPI STATUS REGISTER
22-8
SPSTA0
SPSTA1
Reserved
Data Collision Error Flag
(DCOL)
Multi Master Error Flag
(MULF)
Transfer Ready Flag
(REDY)
Register
SPSTAn
0x59000004
0x59000024
Address
[7:3]
Bit
[2]
[1]
[0]
This flag is set if the SPTDATn is written or the SPRDATn is
read while a transfer is in progress and cleared by reading
the SPSTAn.
0 = not detect,
This flag is set if the nSS signal goes to active low while the
SPI is configured as a master, and SPPINn's ENMUL bit is
multi master errors detect mode. MULF is cleared by
reading SPSTAn.
0 = not detect,
This bit indicates that SPTDATn or SPRDATn is ready to
transmit or receive. This flag is automatically cleared by
writing data to SPTDATn.
0 = not ready,
R/W
R
R
SPI channel 0 status register
SPI channel 1 status register
Description
1 = data Tx/Rx ready
1 = collision error detect
1 = multi master error detect
Description
Reset Value
Initial State
S3C2410A
0x01
0x01
0
0
1