s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 474

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

IIS-BUS INTERFACE
IIS FIFO CONTROL (IISFCON) REGISTER
NOTES:
1.
2.
IIS FIFO (IISFIFO) REGISTER
IIS bus interface contains two 64-byte FIFO for the transmit and receive mode. Each FIFO has 16-width and 32-depth
form, which allows the FIFO to handles data for each halfword unit regardless of valid data size. Transmit and receive
FIFO access is performed through FIFO entry; the address of FENTRY is 0x55000010.
NOTES:
1.
2.
21-8
IISFCON
Transmit FIFO access mode
select
Receive FIFO access mode
select
Transmit FIFO
Receive FIFO
Transmit FIFO data count
(Read only)
Receive FIFO data count
(Read only)
IISFIFO
FENTRY
Register
Register
The IISFCON register is accessible for each halfword and word unit using STRH/STR and LDRH/LDR instructions or
short int/int type pointer in Little/Big endian mode.
(Li/HW/W): Little/HalfWord/Word.
(Bi/HW/W): Big/HalfWord/Word.
The IISFIFO register is accessible for each halfword and word unit using STRH and LDRH instructions or short int type
pointer in Little/Big endian mode.
(Li/HW): Little/HalfWord.
(Bi/HW): Big/HalfWord.
IISFIFO
IISFCON
0x5500000C (Li/HW, Li/W, Bi/W)
0x5500000E (Bi/HW)
0x55000010(Li/HW)
0x55000012(Bi/HW)
[15:0]
Bit
Address
Address
Transmit/Receive data for IIS
[11:6]
[5:0]
[15]
[14]
[13]
[12]
Bit
0 = Normal
1 = DMA
0 = Normal
1 = DMA
0 = Disable
0 = Disable
Data count value = 0 ~ 32
Data count value = 0 ~ 32
R/W
R/W
R/W
R/W
Description
1 = Enable
1 = Enable
IIS FIFO interface register
IIS FIFO register
Description
Description
Description
Reset Value
Reset Value
Initial State
Initial State
000000
000000
S3C2410A
0x0
0x0
0x0
0
0
0
0