s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 207

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

REFRESH CONTROL REGISTER
S3C2410A
REFEN
TREFMD
Trp
Tsrc
Reserved
Reserved
Refresh
Counter
REFRESH
REFRESH
Register
[21:20]
[19:18]
[17:16]
[15:11]
[10:0]
[23]
[22]
Bit
0x48000024
SDRAM Refresh Enable
0 = Disable
SDRAM Refresh Mode
0 = Auto Refresh
In self-refresh time, the SDRAM control signals are driven to the
appropriate level.
SDRAM RAS pre-charge Time
SDRAM Semi Row Cycle Time
00 = 4 clocks 01 = 5 clocks 10 = 6 clocks 11 = 7 clocks
SDRAM's Row-Cycle time(Trc) = Tsrc + Trp
Not used
Not used
SDRAM refresh count value.
Refresh period = (2
Ex) If refresh period is 15.6 us and HCLK is 60 MHz,
Address
00 = 2 clocks
If) Trp=3 clocks & Tsrc=7 clocks, Trc = 3 + 7 = 10 clocks
the refresh count is as follows:
Refresh count = 2
R/W
R/W
01 = 3 clocks
11
-refresh_count+1)/HCLK
11
1 = Self Refresh
+ 1 - 60x15.6 = 1113
Description
1 = Enable (self/auto refresh)
SDRAM refresh control register
10 = 4 clocks
Description
11 = Not support
MEMORY CONTROLLER
Reset Value
0xac0000
Initial State
0000
10
11
00
1
0
0
5-17