s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 130

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM INSTRUCTION SET
USE OF R15
Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction.
DATA ABORTS
If the address used for the swap is unacceptable to a memory management system, the memory manager can flag
the problem by driving ABORT HIGH. This can happen on either the read or the write cycle (or both), and in either
case, the Data Abort trap will be taken. It is up to the system software to resolve the cause of the problem, then the
instruction can be restarted and the original program continued.
INSTRUCTION CYCLE TIMES
Swap instructions take 1S + 2N +1I incremental cycles to execute, where S,N and I are defined as sequential
(S-cycle), non-sequential, and internal (I-cycle), respectively.
ASSEMBLER SYNTAX
<SWP>{cond}{B} Rd,Rm,[Rn]
{cond}
{B}
Rd,Rm,Rn
Examples
3-48
SWP
SWPB
SWPEQ
Two-character condition mnemonic. See Table 3-2.
If B is present then byte transfer, otherwise word transfer
Expressions evaluating to valid register numbers
R0,R1,[R2]
R2,R3,[R4]
R0,R0,[R1]
; Load R0 with the word addressed by R2, and
; store R1 at R2.
; Load R2 with the byte addressed by R4, and
; store bits 0 to 7 of R3 at R4.
; Conditionally swap the contents of the
; word addressed by R1 with R0.
S3C2410A