s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 114

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM INSTRUCTION SET
ASSEMBLER SYNTAX
<LDR|STR>{cond}{B}{T} Rd,<Address>
where:
LDR
STR
{cond}
{B}
{T}
Rd
Rn and Rm
<Address>can be:
1
2
3
<shift>
{!}
3-32
Load from memory into a register
Store from a register into memory
Two-character condition mnemonic. See Table 3-2.
If B is present then byte transfer, otherwise word transfer
If T is present the W bit will be set in a post-indexed instruction, forcing non-
privileged mode for the transfer cycle. T is not allowed when a pre-indexed
addressing mode is specified or implied.
An expression evaluating to a valid register number.
Expressions evaluating to a register number. If Rn is R15 then the assembler will
subtract 8 from the offset value to allow for ARM920T pipelining. In this case base write-
back should not be specified.
An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base and a
corrected immediate offset to address the location given by evaluating the expression.
This will be a PC relative, pre-indexed address. If the address is out of range, an error
will be generated.
A pre-indexed addressing specification:
[Rn]
[Rn,<#expression>]{!}
[Rn,{+/-}Rm{,<shift>}]{!}
A post-indexed addressing specification:
[Rn],<#expression>
[Rn],{+/-}Rm{,<shift>}
General shift operation (see data processing instructions) but you cannot specify the shift
amount by a register.
Writes back the base register (set the W bit) if! is present.
offset of zero
offset of <expression> bytes
offset of +/- contents of index register, shifted
by <shift>
offset of <expression> bytes
offset of +/- contents of index register, shifted as
by <shift>.
S3C2410A