peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 53

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

DMA-Interface
To support efficient data exchange between system memory and the FIFOs an
additional DMA-interface is provided. The FIFOs have separate DMA-request lines
(DRQRA/B for RFIFO, DRQTA/B for XFIFO) and a common DMA-acknowledge input.
The DMA-controller has to operate in the level triggered, demand transfer mode. If the
DMA-controller provides a DMA-acknowledge signal, each bus cycle implicitly selects
the top of FIFO and neither address nor chip select is evaluated. If no DACK signal is
supplied, normal read/write operations (providing addresses) must be performed
(memory to memory transfer).
The SACCO activates the DRQT/R-lines as long as data transfers are needed from/to
the specific FIFOs.
A special timing scheme is implemented to guarantee safe DMA-transfers regardless of
DMA-controller speed.
If in transmit direction a DMA-transfer of n bytes is necessary (n < 32 or the remainder
of a long message), the DRQT-pin is active up to the rising edge of WR of DMA-transfer
(n-1). If n > 32 the same behavior applies additionally to transfers 31, 63, …,
((k × 32) −1). DRQT is activated again with the next rising edge of DACK (or CSS), if
there are further bytes to transfer (Figure 2-3). When a fast DMA-controller is used
(> 16 MHz), byte n (or bytes k × 32) will be transferred before DRQT is deactivated from
the SACCO. In this case pin DRQT is not activated any more up to the next block transfer
(Figure 2-2).
Figure 2-2
Semiconductor Group
Timing Diagram for DMA-Transfers (fast) Transmit (n < 32,
remainder of a long message or n = k × 32)
DRQT
WR
CSS,
DACK
Cycle
n-2
2-7
n-1
n
Functional Block Description
ITD05825
PEB 20560
2003-08