peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 337

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
5.1.2.6
Access: write
Reset value: 00
Note: The maximum time between writing to the CMDR-register and the execution of the
RMC
RHR
AREP/
XREP
bit 7
RMC
command is 2 bits clocks. Therefore, if the CPU operates with a very high clock
speed in comparison to the SACCO-clock, it is recommended that the bit
STAR:CEC is checked before writing to the CMDR-register to avoid loosing of
commands.
Command Register (CMDR)
After a RFS-interrupt the contents of
•
•
•
are valid and can by read by the CPU.
The RFS-interrupt is maskable by programming bit CCR2:RIE.
Receive Message Complete.
A ‘1’ confirms, that the actual frame or data block has been fetched following
a RPF- or RME-interrupt, thus the occupied space in the RFIFO can be
released.
Reset HDLC-Receiver.
A ‘1’ deletes all data in the RFIFO and in the HDLC-receiver.
Auto Repeat/Transmission Repeat.
•
• Extended transparent mode 0,1: XREP
RHCR
RAL1
RSTA bit3-0
RHR
Together with XTF- and XME-set (CMDR = 2A
transmits the contents of the XFIFO (1…32 bytes) fully transparent
without HDLC-framing, i.e. without flag, CRC-insertion, bit stuffing.
The cyclical transmission continues until the command (CMDR:XRES) is
executed or the bit XREP is reset. The inter frame timefill pattern is issued
afterwards.
When resetting XREP, data transmission is stopped after the next XFIFO-
cycle is completed, the XRES-command terminates data transmission
immediately.
Auto-mode: AREP
H
The frame (max. length 32 byte) stored in XFIFO can be polled
repeatedly by the opposite station until the frame is acknowledged.
AREP/
XREP
0
5-94
XPD/
XTF
XDD
Description of Registers
H
) the SACCO repeatedly
XME
PEB 20560
bit 0
XRES
2003-08