peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 152

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
Table 2-25 Specification of the Time-Slot Quadruplet Controlled by Each Bit in
UTSR Bit
TS10
TS11
TS12
TS13
TS14
TS15
2.8.2.6
The function of these two registers is to enable efficient testing of the PEDIU ROM. This
is a 512 word ROM (9 bit address), and it holds linear values of all 8 bits a-law values
and 8-bits µ-low values.
Accessing UPRTAR and UPRTDR is possible only when the PEDIU is in work mode 5 -
testing mode. In this mode the input streams into the PEDIU are not handled by it, so
accessing the PEDIU ROM via these test registers is enabled.
Reading of a PEDIU ROM content is accomplished by writing the 8 lsbs of the demanded
address into UPRTAR, and then reading the 16 bit ROM linear content from UPRTDR.
The msb of the ROM address is the AMUL bit of register UCR (see section 2.8.2.1). This
bit also determines which part of the ROM is being tested - the a-law segment (‘0’) or the
µ-low segment (‘1’).
Address off UPRTAR for read and write: 0xC10B.
bit
UPRTAR
* - Written as “don’t care” and read as ‘0’.
TA7…0
Address off UPRTDR for read only: 0xC10C.
bit
UPRTDR
15
15
PEDIU ROM Test Address Register (UPRTAR) and
PEDIU ROM Test Data Register (UPRTDR)
*
Test Address 8 least significant bits. The most significant bit is determined
by the bit UCR:AMUL (see section 2.8.2.1).
UOSBPER, in the Different Work Modes of the PEDIU (cont’d)
Output Stream
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
*
*
*
Mode 0/1/2
*
Time-Slots
8-11
12-15
16-19
20-23
24-27
28-31
*
2-106
*
TD15…TD0
*
Output Stream
OUT0
OUT0
OUT0
OUT0
OUT0
OUT0
Functional Block Description
TA7…TA0
Mode 3/4
Time-Slots
40-43
44-47
48-51
52-55
56-59
60-63
PEB 20560
2003-08
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