peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 180
peb20560
Manufacturer Part Number
peb20560
Description
Dsp Oriented Pbx Controller Doc
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20560.pdf
(433 pages)
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Semiconductor Group
For Intel type microprocessor systems the 2-cycle interrupt acknowledge scheme is
supported (80x86 mode).
2.13.4.2
If selected via IPC register the Interrupt Enable pins IE0, IE1 are used for building a
Daisy Chain by connecting the Interrupt Enable Output (IE0) of the higher priority device
to the Interrupt Enable Input (IE1) of the lower priority device. The highest priority device
has IE1 pulled high.
Refer to:
Figure 2-50 for interrupt cascading in Siemens/Intel bus mode.
Figure 2-50 Interrupt Cascading (Daisy Chaining) in Siemens/Intel Bus Mode
For Intel type microprocessor systems the 2-cycle interrupt acknowledge scheme is
supported 80X86 mode. Maximum available settling time for the chain: from the
beginning of the first INTA cycle to the beginning of the second.
For Motorola type µP systems the maximum available setting time for the chain is:
from the beginning of the IACK cycle to the falling edge of the RD/DS signal.
Refer to Motorola Timing, Table 7-8.
µ
INTA
P
INT
Daisy Chaining
IE0
DOC
IREQ
IACK
+5 V
IE1
2-134
IE0
DOC
IREQ
IACK
Functional Block Description
IE1
IE0
IREQ
DOC
IACK
PEB 20560
IE1
2003-08
ITS10105
+5 V
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