peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 15

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

List of Figures
Figure 5-4
Figure 5-5
Figure 6-1
Figure 6-2
Figure 6-3
Figure 6-4
Figure 6-5
Figure 6-6
Figure 6-7
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10 PDC and PFS Timing In Master Mode (PDC & PFS are outputs) . . . . 7-15
Figure 7-11 PCM-Interface Timing in Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Figure 7-12 PCM-Interface Timing in Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
Figure 7-13 IOM
Figure 7-14 IOM
Figure 7-15 IOM
Figure 7-16 IOM
Figure 7-17 FSCD timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Figure 7-18 Channel Indication (CHI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27
Figure 7-19 DRDY Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
Figure 7-20 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31
Figure 7-21 Serial Interface Strobe Timing (clock mode 1) . . . . . . . . . . . . . . . . . . . 7-32
Figure 7-22 Serial Interface Synchronization Timing (clock mode 2) . . . . . . . . . . . 7-33
Figure 7-23 DRESET and RESIN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Figure 7-24 Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-35
Figure 7-25 Program Read Access Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Figure 7-26 External RAM Data Read Access Timing Diagram . . . . . . . . . . . . . . . 7-39
Figure 7-27 Emulation Mail-Box Read Access Timing Diagram . . . . . . . . . . . . . . . 7-40
Semiconductor Group
Internal FSC Shift to enable a Synchronization with the
Rising Edge of DCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-36
Use of CTS Signal in SIDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-99
DOC in a Small PBX with 2.048 Mbit/s Data Rate . . . . . . . . . . . . . . . . . 6-2
DOC in a Small PBX with 4.096 Mbit/s Data Rate . . . . . . . . . . . . . . . . . 6-3
DOC on Line Card with 2.048 and 4.096 Mbit/s Data Rates . . . . . . . . . 6-4
DOC on Line Card with 4.096 and 8.192 Mbit/s Data Rates . . . . . . . . . 6-5
Clock Generation in a PBX with one DOC . . . . . . . . . . . . . . . . . . . . . . . 6-6
Clock Synchronization in a PBX with Multiple DOCs . . . . . . . . . . . . . . . 6-7
QUAT-S in LT-T Mode with SIDEC for Four-Channel Trunk
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
I/O-Wave Form for AC-test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Address Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Siemens/Intel Interrupt Timing (Slave mode) . . . . . . . . . . . . . . . . . . . . . 7-8
Siemens/Intel Interrupt Timing (Daisy chaining). . . . . . . . . . . . . . . . . . . 7-9
Motorola Interrupt Timing (Slave mode). . . . . . . . . . . . . . . . . . . . . . . . 7-11
Motorola Interrupt Timing (Daisy chaining) . . . . . . . . . . . . . . . . . . . . . 7-12
Interrupt inactivation from WR, RD. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
ELIC0 and the DOC is in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . 7-21
directly by PDC4/8 and PFS, and the DOC is in Slave Mode . . . . . . . 7-22
Directly by PDC4/8 and PFS, and the DOC is in Master Mode
(PDC and PFS are generated by internal clocks generator) . . . . . . . . 7-24
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
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-2 Interface Clocks Timing When FSC and DCL are Driven by
-2 Interface Clocks Timing When FSC and DCL are Driven
-2 Interface Clocks Timing when FSC and DCL are Driven
-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
I-13
PEB 20560
2003-08
Page