peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 315
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peb20560
Manufacturer Part Number
peb20560
Description
Dsp Oriented Pbx Controller Doc
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20560.pdf
(433 pages)
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Semiconductor Group
RFS
5.1.1.6.6
Access: write
Reset value: 00
Note: The maximum time between writing to the CMDR-register and the execution of the
RMC
Note: In DMA-mode this command is only issued once after a RME-interrupt. The
RHR
AREP/
XREP
bit 7
RMC
command is 2.5 HDC-clock cycles. Therefore, if the CPU operates with a very high
clock speed in comparison to the SACCO-clock, it is recommended that the bit
STAR:CEC is checked before writing to the CMDR-register to avoid loosing of
commands.
SACCO does not generate further DMA requests prior to the reception of this
command.
Command Register (CMDR)
Receive Frame Start.
This is an early receiver interrupt activated after the start of a valid frame has
been detected, i.e. after a valid address check in operation modes providing
address recognition, otherwise after the opening flag (transparent mode 0),
delayed by two bytes.
After a RFS-interrupt the contents of
•
•
•
are valid and can by read by the CPU.
The RFS-interrupt is maskable by programming bit CCR2:RIE.
Receive Message Complete.
A ‘1’ confirms, that the actual frame or data block has been fetched following
a RPF- or RME-interrupt, thus the occupied space in the RFIFO can be
released.
Reset HDLC-Receiver.
A ‘1’ deletes all data in the RFIFO and in the HDLC-receiver.
Auto Repeat/Transmission Repeat.
•
• The frame (max. length 32 byte) stored in XFIFO can be polled repeatedly
• Extended transparent mode 0,1: XREP
RHR
by the opposite station until the frame is acknowledged.
Together with XTF- and XME-set (CMDR = 2A
RHCR
RAL1
RSTA bit3-0
H
Auto-mode: AREP
AREP/
XREP
0
5-72
XPD/
XTF
XDD
Description of Registers
H
) the SACCO repeatedly
XME
PEB 20560
bit 0
XRES
2003-08
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