peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 147

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

2.8.2.3
This register defines:
• Which time-slots, coming in the input streams, will be converted to linear values by the
• Which time-slots will bypass this converter.
The UISBPER is a 16-bit register, where each bit controls 4 sequential time-slots and
determines which time-slots will be converted or not. After setting any of UISBPER bits
to ‘1’, its related 4 sequential time-slots will bypass the a-/µ-law to linear converter. After
resetting any of UISBPER bits (to ‘0’), its related 4 sequential time-slots will be converted
by the a-/µ-law to linear converter.
For each bit in UISBPER
‘0’
‘1’
The PEDIU work mode determines the quadruplet (4 sequential time-slots) that each
UISBPER bit is in charge of. When the PEDIU works in mode 0 or 1 and 2 the UISBPER
is divided into two parts. The 8 lsbs controls the 32 time-slots per frame (when working
in mode 2 these are the first 32 time-slots from 64), coming in IN0 input stream. The
8 msbs controls the 32 time-slots per frame, coming in IN1 input stream. When working
in mode 3 or 4 UISBPER is not divided, and all its 16 bits controls the 64 time-slots,
coming in IN0 input stream. In mode 4 these are the first 64 timeslots from 128.
Table 2-23 describes which time-slot quadruplet is controlled by each UISBPER bit in
each PEDIU work mode.
Table 2-23 Specification of the Time-Slot Quadruplet Controlled by Each Bit in
UISBPER Bit
ISBPE0
ISBPE1
ISBPE2
ISBPE3
Semiconductor Group
15
7
UISBPE15 UISBPE14 UISBPE13 UISBPE12 UISBPE11 UISBPE10
UISBPE7
a-/µ-law to linear converter
Convert the related sequential time-slot quadruplet from a-/µ-law to linear word.
Let the related sequential time-slot quadruple to bypass the a-/µ-law to linear
converter.
PEDIU Input Stream Bypass Enable Register (UISBPER)
14
6
UISBPER, in the Different Work Modes of the PEDIU
UISBPE6
Input Stream
IN0
IN0
IN0
IN0
13
5
UISBPE5
Mode 0/1/2
12
4
UISBPE4
Time-Slots
0-3
4-7
8-11
12-15
2-101
11
3
UISBPE3
Input Stream
IN0
IN0
IN0
IN0
10
2
Functional Block Description
UISBPE2
Mode 3/4
9
1
UISBPE9
UISBPE1
Time-Slots
0-3
4-7
8-11
12-15
PEB 20560
8
0
UISBPE0
UISBPE8
2003-08