peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 197

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Bit 0
IIDB0; IIDB1
IIDB2
Bits 4 and 5
FE
2.14.1.6
This register enables the five types of UART interrupts. Each interrupt can individually
activate the interrupt (INTR) output signal. It is possible to totally disable the interrupt
system by resetting bits 0 through 3 of the interrupt enable register (IER). Similarly,
setting bits of this register to a logic 1 enables the selected interrupt(s). Disabling an
interrupt prevents it from being indicated as active in the IIR and from activating the INTR
output signal. All other system functions operate in their normal manner, including the
setting of the line status and modem status registers.
bit
IER
ERBFI
ETBEI
ERLSI)
EDSSI
Bit 4 through 7
2.14.1.7
This register controls the interface with the modem or data set (or a peripheral device
emulating a modem). The contents of the modem control register (MCR) are indicated
in Table 2-31.
Semiconductor Group
Interrupt Enable Register (IER)
Modem Control Register (MCR)
7
0
This bit can be used in an interrupt environment to indicate whether
an interrupt condition is pending. When bit 0 is a logic 0, an interrupt
is pending and the IIR contents may be used as a pointer to the
appropriate interrupt service routine. When bit 0 is a logic 1, no
interrupt is pending.
These two bits of the IIR are used to identify the highest priority
interrupt pending as indicated in Table 2-36.
In the 16C450 mode this bit is 0. In the FIFO mode this bit is set along
with bit 2 when a time-out interrupt is pending.
These two bits of the IIR are always logic 0.
These two bits are set when FEWO = 1.
This bit enables the received data available interrupt (and time-out
interrupts in the FIFO mode) when set to logic 1.
This bit enables the transmitter holding register empty interrupt when
set to logic 1.
This bit enables the receiver status interrupt when set to logic 1.
This bit enables the modem status interrupt when set to logic 1.
These four bits are always logic 0.
6
0
5
0
4
2-151
0
3
EDSSI
Functional Block Description
2
ERLSI
1
ETBEI
PEB 20560
0
ERBFI
2003-08