peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 292

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

5.1.1.4.27 Timer Register (TIMR)
Access: write
Reset value: 00
The EPIC-1 timer can be used for 3 different purposes: timer interrupt generation
(ISTA:TIG), FSC multiframe generation (CMD2:FC2…0 = 111) and last look period
generation.
SSR
TVAL6…0 Timer Value bits 6…0; the timer period, equal to (1+ TVAL6…0) × 250 µs, is
The timer is started as soon as CMDR:ST is set to 1 and stopped by writing the
TIMR-register or by selecting OMDR:OMS0 = 0.
5.1.1.4.28 Status Register EPIC
Access: read
Reset value: 05
The status register STAR displays the current state of certain events within the EPIC-1.
The STAR register bits do not generate interrupts and are not modified by reading STAR.
MAC
Note: MAC is also set and reset during synchronous transfers.
TAC
PSS
Semiconductor Group
bit 7
bit 7
MAC
SSR
Signaling Sampling Rate.
0…the last look period is defined by TVAL6…0.
1…the last look period is fixed to 125 µs.
programmed here. It can thus be adjusted within the range of 250 µs up to
32 ms.
Memory Access
0…no memory access is in operation.
1…a memory access is in operation. Hence, the memory access registers
may not be used.
Timer Active
0…the timer is stopped.
1…the timer is running.
PCM-Synchronization Status.
1…the PCM-interface is synchronized.
0…the PCM-interface is not synchronized. There is a mismatch between the
TVAL6
TAC
H
H
TVAL5
PSS
®
TVAL4
MFTO
-1 (STAR_E)
5-49
TVAL3
MFAB
TVAL2
MFAE
Description of Registers
TVAL2
MFRW
PEB 20560
bit 0
bit 0
TVAL0
MFFE
2003-08