peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 295

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
Table 5-44 Summary of MF-Channel Commands (cont’d)
Transfer Mode
Transmit + receive
same time-slot
Any # of bytes
1 byte expected
2 bytes expected
8 bytes expected
16 bytes expected
Transmit + receive
same line
1 byte expected
2 bytes expected
8 bytes expected
16 bytes expected
HS:
no HS:
5.1.1.4.30 Interrupt Status Register EPIC
Access: read
Reset value: 00
The ISTA-register should be read after an interrupt in order to determine the interrupt
source.
TIN
SFI
bit 7
TIN
handshake facility enabled (OMDR:MFPS = 1)
handshake facility disable (OMDR:MFPS = 0)
Timer interrupt; a timer interrupt previously requested with CMDR:ST,
TIG = 1 has occurred. The TIN-bit is reset by reading ISTA. It should be
noted that the interrupt generation is periodic, i.e. unless stopped by writing
to TIMR, the ISTA:TIN will be generated each time the timer expires.
Signaling FIFO-Interrupt; this interrupt is generated if there is at least one
valid entry in the CIFIFO indicating a change in a C/I- or SIG-channel.
Reading ISTA does not clear the SFI-bit. Instead SFI is cleared if the CIFIFO
is empty which can be accomplished by reading all valid entries of the
CIFIFO or by resetting the CIFIFO by setting CMDR:CFR to 1.
SFI
H
CMDR:
MFT1,MFT0
10
10
10
10
10
11
11
11
11
MFFI
MAC
MFSAR
00 SAD5…0
00 SAD5…0
01 SAD5…0
10 SAD5…0
11 SAD5…0
00 SAD5…0
01 SAD5…0
10 SAD5…0
11 SAD5…0
5-52
®
-1 (ISTA_E)
PFI
Protocol
Selection
HS
no HS
no HS
no HS
no HS
no HS
no HS
no HS
no HS
PIM
Description of Registers
Application
IOM-2
IOM-1
(IOM-1)
(IOM-1)
(IOM-1)
SLD
SLD
SLD
SLD
SIN
PEB 20560
bit 0
SOV
2003-08