peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 117

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

2.7.6
The DSP performs it’s activities in a cyclic manner, which start with frame sync clock
(FSC). It must finish the execution of the current activities before the beginning of the
next frame sync.
The DSP run time statistics is used by the user to estimate the work load on the DSP.
By using this HW, the user can find very accurately the maximum time spent by the DSP
from the FSC until it finished it’s job.
The DSP statistics include an eight bit counter STATC which is counting up every 1 µs.
Figure 2-38
Usually, the STATC is reset when there is a frame sync (FSC) rising edge. When the
DSP finishes it’s tasks it reads the STATC value.
The time between two consecutive frame syncs is always 125 µs, therefore, if the DSP
is working properly, the counter value should always be less then 125 µs.
If the DSP failed to read the counter value and a new FSC rising edge has arrived, the
counter is not reset. Therefore, the DSP would read a value greater then 125. It means
that the DSP failed to finish it’s tasks within the time frame of 125 µs.
The STATR register is added for helping the user to perform the statistics. STATR is a
general purpose 8-bit read/write register (it’s 8 most significant bits are always read
as ‘0’).
The user program should perform statistics in the following way:
• The STATC is reset upon detection of FSC rising edge.
• The DSP finishes it’s activities and reads the value of STATC and STATR.
• The DSP compares STATC to the previous maximum value saved in STATR.
• If the new value is larger, it should be written to STATR.
The system programmer can get the counter value via µP-Mail Box and thus can change
the DSP program (For example, more conferences may be implemented).
Semiconductor Group
1
Run Time Statistics Counter and Register (STATC and STATR)
µ
s
Reset by FSC of the frame n+1, only if
the DSP has read the counter already
Counter (in Frame n)
STATC
DSP
2-71
Maximum-Value Register
Functional Block Description
STATR
DSP
ITS10076
PEB 20560
2003-08