peb20560 Infineon Technologies Corporation, peb20560 Datasheet - Page 278

• Manufacturer Part Number: peb20560
• Description: Dsp Oriented Pbx Controller Doc
• Manufacturer: Infineon Technologies Corporation

5.1.1.4.10 Configurable Interface Time-Slot Adjustment Register (CTAR)
Access: read/write
Reset value: 00
TSN6…0
Note: If CMD1:CSS = 0, the CFI-frame will be shifted - together with the FSC-output
5.1.1.4.11 Configurable Interface Bit Shift Register (CBSR)
Access: read/write
Reset value: 00
SFSC
Semiconductor Group
bit 7
bit 7
SFSC
0
signal - with respect to PFS. The position of the CFI-frame relative to the
FSC-output signal is not affected by these settings, but is instead determined by
CMD2:FC2..0. If CMD1:CSS = 1, the CFI-frame will be shifted with respect to the
FSC-input signal.
Time-Slot Number.
The CFI-framing signal (PFS if CMD1:CSS = 0 or FSC if CMD1:CSS = 1)
marks the CFI time-slot called TSN according to the following formula:
TSN6…0 = TSN + 2
E.g.: If the framing signal is to mark time-slot 0 (bit 7), CTAR must be set to
02
Shift FSC
0…default (behaviour like EPIC-1 PEB 2055)
1…with double clock rate the FSC input is delayed by one and a half CFI
clock cycle (IOM-2 compatibility)
CDS2
TSN6
H
H
H
(CBSR to 20
CDS1
TSN5
H
).
CDS0
TSN4
5-35
CUS3
TSN3
CUS2
TSN2
Description of Registers
CUS1
TSN1
PEB 20560
bit 0
bit 0
CUS0
TSN0
2003-08