S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 63

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 01/02/02
Symbol
t13
t10
t11
t12
t14
t15
t9
t1
t2
t3
t4
t5
t6
t7
t8
1
2
Symbol
T
t
t
PWH
PWL
OSC
Clock period
Clock pulse width low
Clock pulse width high
ADDR[12:0] setup to first CLK of cycle
ADDR[12:0] hold from command invalid
ADDR[12:0] setup to falling edge ALE
ADDR[12:0] hold from falling edge ALE
-CARDREG hold from command invalid
Falling edge of chip select to -CARDxWAIT driven
Command invalid to -CARDxWAIT tri-state
D[31:16] valid to first CLK of cycle (write cycle)
D[31:16] hold from rising edge of -CARDxWAIT
Chip select to D[31:16] driven (read cycle)
D[31:16] setup to rising edge -CARDxWAIT (read cycle)
Command invalid to D[31:16] tri-state (read cycle)
t
t
f
r
90%
10%
V
V IL
IH
t r
Note
1.
2.
Input Clock Period)
Input Clock Pulse Width High
Input Clock Pulse Width Low
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
The Philips interface has different clock input requirements as follows:
Table 7-9: Clock Input Requirements for BUSCLK using Philips local bus
If the S1D13505 host interface is disabled, the timing for -CARDxWAIT driven is relative to
the falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0]
becomes valid, whichever one is later.
If the S1D13505 host interface is disabled, the timing for D[31:16] driven is relative to the
falling edge of chip select or the second positive edge of DCLKOUT after ADDR[12:0] be-
comes valid, whichever one is later.
Parameter
t
PWH
Parameter
Figure 7-9: Clock Input Requirement
Table 7-8: Philips Timing
T
OSC
t
f
t
PWL
13.3
Min
6
6
13.3
Min
10
10
10
6
6
0
5
0
0
5
0
1
0
5
3.0V
Max
Max
15
25
25
5
5
13.3
Min
2.5
2.5
10
10
10
6
6
0
5
0
0
0
1
0
5.0V
Units
ns
ns
ns
ns
ns
Max
10
10
9
X23A-A-001-14
S1D13505
Units
Page 57
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns