S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 508

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 20
4.6 Test Software
BR4
OR4
MemStart
DisableReg
RevCodeReg
Start
Loop
S1D13505
X23A-G-008-05
equ
equ
equ
equ
equ
mfspr
andis.
andis.
oris
ori
stw
andis.
oris
ori
stw
andis.
oris
stb
lbz
b
end
Note
The test software is very simple. It configures chip select 4 (CS4) on the MPC821 to map
the S1D13505 to an unused 4M byte block of address space. Next, it loads the appropriate
values into the option register for CS4 and writes the value 0 to the S1D13505 register
REG[1Bh] to enable the S1D13505 host interface. Lastly, the software runs a tight loop that
reads the S1D13505 Revision Code Register REG[00h]. This allows monitoring of the bus
timing on a logic analyzer.
The following source code was entered into the memory of the MPC821ADS using the
line-by-line assembler in MPC8BUG (the debugger provided with the ADS board). Once
the program was executed on the ADS, a logic analyzer was used to verify operation of the
interface hardware.
It is important to note that when the MPC821 comes out of reset, the on-chip caches and
MMU are disabled. If the data cache is enabled, then the MMU must be set so that the
S1D13505 memory block is tagged as non-cacheable. This ensures the MPC821 does not
attempt to cache any data read from, or written to, the S1D13505 or its display buffer.
MPC8BUG does not support comments or symbolic equates; these have been added for
clarity.
$120
$124
$40
$1b
0
r1,IMMR
r1,r1,$ffff
r2,r0,0
r2,r2,MemStart
r2,r2,$0801
r2,BR4(r1)
r2,r0,0
r2,r2,$ffc0
r2,r2,$0608
r2,OR4(r1)
r1,r0,0
r1,r1,MemStart
r1,DisableReg(r1) ; write 0 to disable register
r0,RevCodeReg(r1) ; read revision code into r1
Loop
; CS4 base register
; CS4 option register
; upper word of S1D13505 start address
; address of S1D13505 Disable Register
; address of Revision Code Register
; get base address of internal registers
; clear lower 16 bits to 0
; clear r2
; write base address
; port size 16 bits; select GPCM; enable
; write value to base register
; clear r2
; address mask – use upper 10 bits
; normal CS negation; delay CS ½ clock;
; no burst inhibit (13505 does this)
; write to option register
; clear r1
; point r1 to start of S1D13505 mem space
; branch forever
Interfacing to the Motorola MPC821 Microprocessor
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/05