S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 37

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S1D13505

Manufacturer Part Number
S1D13505
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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HRTC
VRTC
RED
GREEN
BLUE
IREF
Epson Research and Development
Vancouver Design Center
5.2.3 LCD Interface
5.2.4 CRT Interface
Hardware Functional Specification
Issue Date: 01/02/02
FPDAT[15:0] O
FPFRAME
FPLINE
FPSHIFT
LCDPWR
DRDY
Pin Name
Pin Name
O
O
O
O
O
Type
IO
IO
O
O
O
I
Type
95-88,
86-79
73
74
77
75
76
Pin #
107
108
100
103
105
101
Pin #
CN3
CN3
CN3
CO3
CO1
CN3
Cell
RESET# State
0utput
0utput
0utput
0utput
0utput if
MD[10]=0
1 if MD[10]=1
0utput
CN3
CN3
A
A
A
A
Cell
Table 5-2: LCD
Table 5-3: CRT Interface Pin Descriptions
0utput
0utput
RESET
# State
Panel data bus. Not all pins are used for some panels - see LCD
Interface Pin Mapping for details. Unused pins are driven low.
Frame pulse
Line pulse
Shift clock
LCD power control output. The active polarity of this output is selected
by the state of MD10 at the rising edge of RESET# - see Summary of
Configuration Options. This output is controlled by the power save
mode circuitry - see Power Save Modes for details.
This is a multi-purpose pin:
• For TFT/D-TFD panels this is the display enable output (DRDY).
• For passive LCD with Format 1 interface this is the 2nd Shift Clock
• For all other LCD panels this is the LCD backplane bias signal
See LCD Interface Pin Mapping and REG[02h] for details.
Horizontal retrace signal for CRT
Vertical retrace signal for CRT
Analog output for CRT color Red
Analog output for CRT color Green
Analog output for CRT color Blue
Current reference for DAC - see Analog Pins. This pin must be left
unconnected if the DAC is not needed.
(FPSHIFT2)
(MOD).
Interface Pin Descriptions
Description
Description
X23A-A-001-14
S1D13505
Page 31

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