S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 120

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 114
bit 7
bits 6-5
S1D13505
X23A-A-001-14
Performance Enhancement Register 0
REG[22h]
Reserved
RC Timing
Value Bit 1
REG[22h] bits [6:5]
Note
Reserved
RC Timing Value (N
These bits select the DRAM random-cycle timing parameter, t
(N
t
value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%.
N
N
The resulting t
t
RAS
RC
00
01
10
11
RC
RC
Changing this register to non-zero value, or to a different non-zero value, should be done only
when there are no read/write DRAM cycles. This condition occurs when all of the following are
true: the Display FIFO is disabled (REG[23h] bit 7 = 1), and the Half Frame Buffer is disabled
(REG[1Bh] bit 0 = 1), and the Ink/Cursor is inactive (Reg[27h] bits 7-6 = 00). This condition also
occurs when the CRT and LCD enable bits (Reg[0Dh] bits 1-0) have remained 0 since chip reset.
For further programming information, see S1D13505 Programming Notes and Examples, docu-
ment number X23A-G-003-xx.
RC
, the RAS pulse width. Use the following two formulae to calculate N
RC Timing
Value Bit 0
) of MCLK periods (T
Table 8-12: Minimum Memory Timing Selection
RC
= Round-Up (t
= Round-Up (t
= Round-Up (t
= (N
is related to N
RC
RC
RAS#-to-
CAS# Delay
Value
) T
) Bits [1:0]
M
M
) used to create t
RC
RAS
RAS
Reserved
RC
/T
N
/T
/T
as follows:
5
4
3
M
RC
M
M
RAS#
Precharge
Timing Value
Bit 1
)
+ N
+ 1.55)
RP
)
RC
. N
RC
if N
if N
RAS#
Precharge
Timing Value
Bit 0
should be chosen to meet t
RP
RP
Minimum Random Cycle
= 1 or 2
= 1.5
RC
Width (
Reserved
. These bits specify the number
Epson Research and Development
Reserved
5
4
3
Hardware Functional Specification
t
RC
RC
)
Vancouver Design Center
then choose the larger
Issue Date: 01/02/02
RC
Reserved
as well as
RW