S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 112

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 106
8.2.4 Display Configuration Registers
bit 7
bits 6-5
S1D13505
X23A-A-001-14
Display Mode Register
REG[0Dh]
SwivelView
Enable
Select Bits [1:0]
Display Option
Simultaneous
00
01
10
11
Simultaneous
Display
Option Select
Bit 1
Even Scan Only
Simultaneous
Display Mode
Line Doubling
Interlace
Normal
Note
SwivelView Enable
When this bit = 1, all CPU accesses to the display buffer are translated to provide clockwise 90°
hardware rotation of the display image. Refer to “Section 13 SwivelView” for application and limi-
tations.
Simultaneous Display Option Select Bits [1:0]
These bits are used to select one of four different simultaneous display mode options: Normal, Line
Doubling, Interlace, or Even Scan Only. The purpose of these modes is to manipulate the vertical
resolution of the image so that it fits on both the CRT, typically 640x480, and LCD. The following
table describes the four modes using a 640x480 CRT as an example:
1. Dual Panel Considerations: When configured for a dual LCD panel and using
2. The Line doubling option is not supported with dual panel.
Simultaneous
Display
Option Select
Bit 0
Simultaneous Display, the Half Frame Buffer Disable, REG[1Bh] bit 0, must be set to 1.
This results in a lower contrast on the LCD panel, which may require adjustment.
The image is not manipulated. This mode is used when the CRT and LCD have the same
resolution, e.g. 480 lines.
It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD
duty cycle
lower contrast on the LCD.
Each line is replicated on the CRT. This mode is used to display a 240-line image on a
240-line LCD and stretch it to a 480-line image on the CRT. The CRT has a heightened
aspect ratio.
It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD
duty cycle
and the contrast of the LCD image should not be greatly reduced.
The odd and even fields of a 480-line image are interlaced on the LCD. This mode is used
to display a 480-line image on the CRT and squash it onto a 240-line LCD. The full image
is viewed on the LCD but the interlacing may create flicker. The LCD has a shortened
aspect ratio.
It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD
duty cycle (2/525 compared to the usual 1/241). This reduced duty cycle is not extreme
and the contrast of the LCD image should not be greatly reduced.
Only the even field of a 480-line image is displayed on the LCD. This is an alternate
method to display a 480-line image on the CRT and squash it onto a 240-line LCD. Only
the even scans are viewed on the LCD. The LCD has a shortened aspect ratio.
It is necessary to suit the vertical retrace period to the CRT. This results in a lower LCD
duty cycle
and the contrast of the LCD image should not be greatly reduced.
Table 8-6: Simultaneous Display Option Selection
(
(
(
1/525 compared to the usual 1/481). This reduced duty cycle may result in
2/525 compared to the usual 1/241). This reduced duty cycle is not extreme
2/525 compared to the usual 1/241). This reduced duty cycle is not extreme
Bit-per-pixel
Select Bit 2
Bit-per-pixel
Select Bit 1
Mode Description
Bit-per-pixel
Select Bit 0
Epson Research and Development
CRT Enable
Hardware Functional Specification
Vancouver Design Center
Issue Date: 01/02/02
LCD Enable
RW