S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 482

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 10
3 S1D13505 Host Bus Interface
3.1 Host Bus Interface Pin Mapping
S1D13505
X23A-G-007-06
Note
The S1D13505 directly supports multiple processors. The S1D13505 implements a 16-bit
MIPS/ISA Host Bus Interface which is most suitable for direct connection to the
VR4102/VR4111 microprocessor.
The MIPS/ISA host bus interface is selected by the S1D13505 on the rising edge of
RESET#. After releasing reset the bus interface signals assume their selected configuration.
For details on S1D13505 configuration, see Section 4.2, “S1D13505 Hardware Configu-
ration” on page 13.
The following table shows the functions of each host bus interface signal.
At reset, the Host Interface Disable bit in the Miscellaneous Disable Register
(REG[1Bh] bit 7) is set to 1. This means that only REG[1Ah] (read-only) and
REG[1Bh] are accessible until a write to REG[1Bh] sets bit 7 to 0 making all regis-
ters accessible. When debugging a new hardware design, this can sometimes give the
appearance that the interface is not working, so it is important to remember to clear this
bit before proceeding with debugging.
S1D13505 Pin Name
BUSCLK
RD/WR#
Table 3-1: Host Bus Interface Pin Mapping
AB[19:0]
DB[15:0]
RESET#
WAIT#
WE1#
WE0#
AB20
M/R#
CS#
RD#
BS#
NEC VR4102/VR4111 Pin Name
connected to system reset
Connected to V
Connected to V
ADD[19:0]
DAT[15:0]
LCDRDY
LCDCS#
BUSCLK
ADD20
ADD21
SHB#
WR#
RD#
Interfacing to the NEC VR4102/VR4111™ Microprocessors
DD
DD
Epson Research and Development
Vancouver Design Center
Issue Date: 01/02/05