S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 245

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Programming Notes and Examples
Issue Date: 01/02/05
** Register A: Vertical Non-Display Period (VNDP)
**
**
**
*/
*(pRegs + 0x0A) = 0x01;
/*
** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only.
*/
*(pRegs + 0x0B) = 0x00;
/*
** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only.
*/
*(pRegs + 0x0C) = 0x00;
/*
** Register D: Display Mode - 8 BPP, LCD disabled.
*/
*(pRegs + 0x0D) = 0x0C;
/*
** Registers E-F: Screen 1 Line Compare - unless setting up for
**
*/
*(pRegs + 0x0E) = 0xFF;
*(pRegs + 0x0F) = 0x03;
/*
** Registers 10-12: Screen 1 Display Start Address - start at the
**
*/
*(pRegs + 0x10) = 0x00;
*(pRegs + 0x11) = 0x00;
*(pRegs + 0x12) = 0x00;
/*
** Register 13-15: Screen 2 Display Start Address - not applicable
**
*/
*(pRegs + 0x13) = 0x00;
*(pRegs + 0x14) = 0x00;
*(pRegs + 0x15) = 0x00;
/*
** Register 16-17: Memory Address Offset - this address represents the
**
**
*/
*(pRegs + 0x16) = 0x40;
*(pRegs + 0x17) = 0x01;
/*
** Register 18: Pixel Panning
*/
*(pRegs + 0x18) = 0x00;
This register must be programed with register 5 (HNDP)
to arrive at the frame rate closest to the desired
frame rate.
split screen operation use 0x3FF.
unless setting up for split screen operation.
starting WORD. At 8BPP our 640 pixel width is 320
WORDS
first byte in display memory.
/* 0000 0001 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 1100 */
/* 1111 1111 */
/* 0000 0011 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0000 0000 */
/* 0100 0000 */
/* 0000 0001 */
/* 0000 0000 */
X23A-G-003-07
S1D13505
Page 91