S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 167

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
Programming Notes and Examples
Issue Date: 01/02/05
Register
[0C]
[0D]
[1C]
[1D]
[0A]
[0B]
[0E]
[0F]
[1A]
[1E]
[1F]
[06]
[07]
[08]
[09]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
0000 0000
0000 0000
1110 1111
0000 0000
0011 1000
0000 0000
0000 0000
0000 1100
1111 1111
0000 0011
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0100 0000
0000 0001
0000 0000
0000 0001
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Value
FPLINE start position - only required for CRT or TFT/D-TFD
FPLINE polarity set to active high
Vertical display size = Reg[09][08] + 1
= 0000 0000 1110 1111 + 1
= 239+1 = 240 lines (total height/2 for dual panels)
Vertical non-display size = Reg[0A] + 1 = 57 + 1 = 58 lines
FPFRAME start position - only required for CRT or TFT/D-TFD
FPFRAME polarity set to active high
Display mode - hardware portrait mode disabled, 8 bpp and
LCD disabled, enable LCD in last step of this example.
Line compare (Regs[0Eh] and[0Fh] set to maximum allowable
value. We can change this later if we want a split screen.
Screen 1 Start Address (Regs [10h], [11h], and [12h]) set to 0.
This will start the display in the first byte of the display buffer.
Screen 2 Start Address (Regs [13h], [14h], and [15h]) to offset
0. Screen 2 Start Address in not used at this time.
Memory Address Offset (Regs [17h] [16h])
- 640 pixels = 640 bytes = 320 words = 140h words
Note: When setting a horizontal resolution greater than 767
pixels, with a color depth of 15/16 bpp, the Memory Offset
Registers (REG[16h], REG[17h]) must be set to a virtual
horizontal pixel resolution of 1024.
Set pixel panning for both screens to 0
Clock Configuration - set PClk to MClk/2 - the specification says
that for a dual color panel the maximum PClk is MClk/2
Enable LCD Power
MD Configuration Readback - we write a 0 here to keep the
register configuration logic simpler
General I/O Pins - set to zero.
General I/O Pins Control - set to zero.
Table 2-1: S1D13505 Initialization Sequence (Continued)
Notes
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See Also
X23A-G-003-07
S1D13505
Page 13