S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 194

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 40
6.2 Software Power Save
S1D13505
X23A-G-003-07
Delay Too Long
To shorten 128 frame delay on LCDPWR.
1. Set REG[23h] bit 7 to 1 - Blanks screen by disabling the FIFO.
2. Set REG[04h] to 3 (changes display width to 32 pixels)
3. Set REG[1Ah] bit 0 to 0 - Enables power save mode.
4. Wait delay time (based on new frame rate, see S1D13505 Hardware Functional Spec-
5. Enable any clocks that were disabled in step 4.
6. Set REG[1Ah] bit 0 to 0 - Disables power save mode.
7. Set REG[04h] to original setting
8. Set REG[023h] bit 7 to 0 - Un-blanks screen by enabling the FIFO.
The S1D13505 supports a software initiated suspend power save mode. This mode is
controllable using the Software Suspend Mode Enable bit in REG[1Ah]. The type of
memory refresh used during suspend can also be controlled by software.
While software suspend is enabled the following conditions apply.
• display(s) are inactive
• registers are accessible
• memory is not-accessible
• LUT is accessible
Set REG[08h] to 0 (changes display height to 1 line)
- This changes the display resolution to minimum (32x1).
ification, document number X23A-A-001-xx)
.
.
.
Set REG[08h] to original setting
- Re-initializes the original resolution.
- at this time any clocks can be disabled.
Epson Research and Development
Programming Notes and Examples
Vancouver Design Center
Issue Date: 01/02/05