S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 499

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
2.3 Memory Controller Module
2.3.1 General-Purpose Chip Select Module (GPCM)
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 01/02/05
If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI)
simultaneously with TA, and the processor will revert to normal bus cycles for the
remaining data transfers.
Burst cycles are mainly intended to facilitate cache line fills from program or data memory.
They are normally not used for transfers to/from IO peripheral devices such as the
S1D13505, therefore the interfaces described in this document do not attempt to support
burst cycles. However, the example interfaces include circuitry to detect the assertion of
BDIP and respond with BI if caching is accidently enabled for the S1D13505 address space.
The General-Purpose Chip Select Module (GPCM) is used to control memory and
peripheral devices which do not require special timing or address multiplexing. In addition
to the chip select output, it can generate active-low Output Enable (OE) and Write Enable
(WE) signals compatible with most memory and x86-style peripherals. The MPC821 bus
controller also provides a Read/Write (RD/WR) signal which is compatible with most 68K
peripherals.
The GPCM is controlled by the values programmed into the Base Register (BR) and Option
Register (OR) of the respective chip select. The Option Register sets the base address, the
block size of the chip select, and controls the following timing parameters:
• The ACS bit field allows the chip select assertion to be delayed by 0, ¼, or ½ clock
• The CSNT bit causes chip select and WE to be negated ½ clock cycle earlier than
• The TRLX (relaxed timing) bit will insert an additional one clock delay between
• The EHTR (Extended hold time) bit will insert an additional 1 clock delay on the first
• Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself
• Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its
cycle with respect to the address bus valid.
normal.
assertion of the address bus and chip select. This accommodates memory and
peripherals with long setup times.
access to a chip select.
by asserting TA (Transfer Acknowledge).
memory space is addressed by the processor core.
X23A-G-008-05
S1D13505
Page 11