S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 149

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
14.3 Bandwidth Calculation
Bandwidth during non display period
Bandwidth during display period
Hardware Functional Specification
Issue Date: 01/02/02
When calculating the average bandwidth, there are two periods that must be calculated separately.
The first period is the time when the CPU is in competition with the display refresh fetches. The CPU
can only access the memory when the display refresh releases the memory controller. The CPU
bandwidth during this period is called the “bandwidth during display period”.
The second period is the time when the CPU has full access to the memory, with no competition from
the display refresh. The CPU bandwidth during this period is called the “bandwidth during non
display period.”
To calculate the average bandwidth, calculate the percentage of time between display period and non
display period. The percentage of display period is multiplied with the bandwidth during display
period. The percentage of non display period is multiplied with the bandwidth during non display
period. The two products are summed to provide the average bandwidth.
Based on simulation, it requires a minimum of 12 MCLKs to service one, two byte, CPU access to
memory. This includes all the internal handshaking and assumes that N
wait state bits are set to 10b.
The amount of time taken up by display refresh fetches is a function of the color depth, and the
display type. Below is a table of the number of MCLKs required for various memory fetches to
display 16 pixels. Assuming N
4.
5.
6.
Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too
high for a panel, MCLK should be reduced or PCLK should be divided down.
Half Frame Buffer disabled by REG[1Bh] bit 0.
When setting a horizontal resolution greater than 767 pixels, with a color depth of 15/16 bpp,
the Memory Offset Registers (REG[16h], REG[17h]) must be set to a virtual horizontal pixel
resolution of 1024.
Table 14-4: Number of MCLKs required for various memory access
Half Frame Buffer, monochrome
Bandwidth during non display period = f(MCLK) / 6 Mb/s
Half Frame Buffer, color
Display @ 16 bpp
Memory access
Display @ 1 bpp
Display @ 2 bpp
Display @ 4 bpp
Display @ 8 bpp
CPU
RC
= 4MCLKs.
Number of MCLKs
11
11
19
7
4
5
7
4
RC
is set to 4MCLKs and the
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