S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 122

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 116
bits 1-0
bit 0
bit 7
S1D13505
X23A-A-001-14
Performance Enhancement Register 1
REG[23h]
Display FIFO
Disable
DRAM Type
CPU to
Memory Wait
State
Bit 1
EDO
FPM
REG[22h] bits [3:2]
Note
Reserved
These bits must be set to 0.
Optimal DRAM Timing
The following table contains the optimally programmed values of N
DRAM types, at maximum MCLK frequencies.
Table 8-15: Optimal N
Reserved
This reserved bit must be set to 0.
Display FIFO Disable
When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e., the
screen is blanked). This accelerates screen updates by allocating more memory bandwidth to CPU
accesses.
When this bit = 0 the display FIFO is enabled.
00
01
10
11
For further performance increase in dual panel mode disable the half frame buffer (see section
8.2.7) and disable the cursor (see section 8.2.9).
DRAM Speed
CPU to
Memory Wait
State
Bit 0
(ns)
50
60
70
60
70
Table 8-14: RAS Precharge Timing Select
RC
Display FIFO
Threshold
Bit 4
, N
RP
(ns)
T
25
30
40
50
33
, and N
M
Reserved
N
RCD
1.5
2
1
RP
Display FIFO
Threshold
Bit 3
values at maximum MCLK frequency
(#MCLK)
N
4
4
5
4
3
RC
Display FIFO
Threshold
Bit 2
RAS# Precharge Width (t
(#MCLK)
N
1.5
1.5
1.5
1.5
2
RP
Reserved
Epson Research and Development
RC
1.5
2
1
Display FIFO
Threshold
Bit 1
Hardware Functional Specification
, N
RP
(#MCLK)
N
, and N
Vancouver Design Center
RCD
2
2
2
2
1
Issue Date: 01/02/02
RP
RCD
)
Display FIFO
Threshold
Bit 0
for different
RW