S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 262

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 108
S1D13505
X23A-G-003-07
REG[0Dh]
REG[02h]
REG[03h]
REG[04h]
REG[05h]
REG[08h]
REG[09h]
REG[0Ah]
REG[19h]
REG[1Bh]
REG[24h]
REG[26h]
Register
Mono 4-Bit EL
640X480@60Hz
1000 0010
0000 0000
0100 1111
0000 0101
1110 1111
0000 0000
0011 1110
0000 1101
0000 0010
0000 0000
0000 0000
load LUT
Table 12-4: TFT Single Panel @ 640x480 with 25.175 MHz Pixel Clock
Table 12-3: Passive Dual Panel @ 640x480 with 40MHz Pixel Clock
REG[0Ch]
REG[0Dh]
REG[0Ah]
REG[0Bh]
REG[1Bh]
REG[02h]
REG[03h]
REG[04h]
REG[05h]
REG[06h]
REG[07h]
REG[08h]
REG[09h]
REG[19h]
REG[24h]
REG[26h]
Register
640X480@60Hz
Mono 8-Bit
0001 0010
0000 0000
0100 1111
0000 0101
1110 1111
0000 0000
0011 1110
0000 1101
0000 0010
0000 0000
0000 0000
load LUT
640X480@60Hz
Color 16-Bit
0010 0101
0000 0000
0100 1111
0001 0011
0000 0001
0000 1011
1101 1111
0000 0001
0010 1011
0000 1001
0000 0001
0000 1101
0000 0000
0000 0001
0000 0000
load LUT
640X480@60Hz
Color 8-Bit
0001 0110
0000 0000
0100 1111
0000 0101
1110 1111
0000 0000
0011 1110
0000 1101
0000 0010
0000 0000
0000 0000
load LUT
set HSYNC polarity and pulse width
set VSYNC polarity and pulse width
set vertical display height bits 7-0
set vertical display height bits 9-8
set horizontal non-display period
set Look-Up Table address to 0
set vertical non-display period
set MCLK and PCLK divide
set horizontal display width
set 8 bpp and LCD enable
set HSYNC start position
set VSYNC start position
disable half frame buffer
640X480@60Hz
Color 16-Bit
load Look-Up Table
0010 0110
0000 0000
0100 1111
0000 0101
1110 1111
0000 0000
0011 1110
0000 1101
0000 0010
0000 0000
0000 0000
load LUT
set panel type
set MOD rate
Notes
set vertical display height bits 7-0
set vertical display height bits 9-8
set horizontal non-display period
set Look-Up Table address to 0
set vertical non-display period
set MCLK and PCLK divide
set horizontal display width
set 8 bpp and LCD enable
enable half frame buffer
load Look-Up Table
Epson Research and Development
set panel type
set MOD rate
Programming Notes and Examples
Notes
Vancouver Design Center
Issue Date: 01/02/05