S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 169

no-image

S1D13505

Manufacturer Part Number
S1D13505
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S1D13505F00A
Manufacturer:
EPSON
Quantity:
254
Part Number:
S1D13505F00A100
Manufacturer:
EPSON
Quantity:
8 000
Part Number:
S1D13505F00A2
Manufacturer:
EPSON
Quantity:
5
Part Number:
S1D13505F00A2
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Part Number:
S1D13505F00A200
Manufacturer:
EPSON
Quantity:
1 400
Part Number:
S1D13505F00A200
Manufacturer:
Epson Electronics America Inc-Semiconductor Div
Quantity:
10 000
Part Number:
S1D13505F00A200
Manufacturer:
EPSON/爱普生
Quantity:
20 000
Epson Research and Development
Vancouver Design Center
2.1 Miscellaneous
Display FIFO Threshold
Memory Address Offset
Half Frame Buffer Disable
Programming Notes and Examples
Issue Date: 01/02/05
This section of the notes contains recommendations which can be set at initialization time
to improve display image quality.
At high color depths the display FIFO introduces two conditions which must be accounted
for in software. Simultaneous display while using a dual passive panel introduces another
possible register change.
At 15/16 bit-per-pixel the display FIFO threshold (bits 0-4 of register [23h]) must be
programmed to a value other than '0'. Product testing has shown that at these color depths
a better quality image results when the display FIFO threshold is set to a value of 1Bh.
When an 800x600 display mode is selected at 15 or 16 bpp, memory page breaks can
disrupt the display buffer fetches. This disruption produces a visible flicker on the display.
To avoid this set the Memory Address Offset (Reg [16h] and Reg [17h]) to 200h. This sets
a 1024 pixel line which aligns the memory page breaks and reduces any flicker.
The half frame buffer stores the display data for dual drive LCD panels. During LCD only
or simultaneous display using a single LCD panel, no special adjustments are required.
However, for simultaneous display using a dual drive LCD panel, the half frame buffer
must be disabled (REG[1Bh] bit 0 = 1). This results in reduced contrast on the LCD panel
because the duty cycle of the LCD is halved. To compensate for this change, the pattern
used by the Frame Rate Modulator (FRM) may need to be adjusted. Programming the
Alternate FRM Register (REG[31h]) with the recommended value of FFh may produce
more visually appealing output.
For further information on the half frame buffer and the Alternate FRM Register see the
S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
X23A-G-003-07
S1D13505
Page 15

Related parts for S1D13505