S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 116

• Manufacturer Part Number: S1D13505
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Page 110
8.2.5 Clock Configuration Register
bit 7
bit 2
bits 1-0
8.2.6 Power Save Configuration Registers
bit 7
S1D13505
X23A-A-001-14
Clock Configuration Register
REG[19h]
Reserved
Power Save Configuration Register
REG[1Ah]
Power Save
Status
RO
n/a
n/a
PCLK Divide Select Bits [1:0]
Note
Reserved
This bit must be set to 0.
MCLK Divide Select
When this bit = 1 the MCLK frequency is half of its source frequency.
When this bit = 0 the MCLK frequency is equal to its source frequency.
The MCLK frequency should always be set to the maximum frequency allowed by the DRAM; this
provides maximum performance and minimum overall system power consumption.
PCLK Divide Select Bits [1:0]
These bits select the MCLK: PCLK frequency ratio
See section on “Maximum MCLK:PCLK Frequency Ratios” for selection of clock ratios.
Power Save Status
This is a read-only status bit.
This bit indicates the power-save state of the chip.
When this bit = 1, the panel has been powered down and the memory controller is either in self
refresh mode or is performing only
When this bit = 0, the chip is either powered up, in transition of powering up, or in transition of
powering down. See Section 15 Power Save Modes for details.
There must always be a source clock at CLKI.
n/a
n/a
00
01
10
11
Table 8-9: PCLK Divide Selection
n/a
n/a
CAS-before-RAS
n/a
LCD Power
Disable
MCLK: PCLK Frequency Ratio
MCLK Divide
Select
Suspend
Refresh
Select Bit 1
refresh cycles.
1: 1
2: 1
3: 1
4: 1
Epson Research and Development
Suspend
Refresh
Select Bit 0
PCLK Divide
Select Bit 1
Hardware Functional Specification
Vancouver Design Center
Issue Date: 01/02/02
PCLK Divide
Select Bit 0
Software
Suspend
Mode Enable
RW
RW