S1D13505 Epson Electronics America, Inc., S1D13505 Datasheet - Page 542

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S1D13505

Manufacturer Part Number
S1D13505
Description
LCD Controller
Manufacturer
Epson Electronics America, Inc.
Datasheet

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Page 12
4 V
4.1 Hardware Description
S1D13505
X23A-G-011-04
R
4121 to S1D13505 Interface
NEC V
ADD[25:0]
R
DAT[15:0]
LCDRDY
BUSCLK
4121
LCDCS#
SHB#
V
V
WR#
RD#
DD
DD
Note:
When connecting the S1D13505 RESET# pin, the system designer should be aware of all
conditions that may reset the S1D13505 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Note
The NEC V
controller. It provides all the necessary internal address decoding and control signals
required by the S1D13505.
The diagram below shows a typical implementation utilizing the S1D13505.
3
2
Figure 4-1: NEC V
For pin mapping see Table 3-1:, “Host Bus Interface Pin Mapping,” on page 10.
+3.3V
+2.5V
R
4121 microprocessor is specifically designed to support an external LCD
ADD21
R
4121 to S1D13505 Configuration Schematic
System RESET
Pull-up
Interfacing to the NEC VR4121™ Microprocessor
V
DD
(+3.3V)
Epson Research and Development
S1D13505
WE0#
WE1#
RD#
CS#
WAIT#
M/R#
AB[20:0]
DB[15:0]
BUSCLK
BS#
RD/WR#
V
RESET#
DD
Vancouver Design Center
Issue Date: 01/02/05

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